FIG. 10 is a cross-sectional view schematically showing a structure of a field effect transistor type semiconductor device according to related art using a group III nitride-based semiconductor. Such a field effect transistor type semiconductor device has been reported, for example, by Imanaga et al. (see Patent Document 1).
The field effect transistor type semiconductor device shown in FIG. 10 comprises, for example, constitutions described below. A substrate 100 is a substrate having a (0001) plane, i.e. a C-plane, a buffer layer 101 is made of undoped gallium nitride (GaN) or aluminum gallium nitride (AlGaN), an electron supply layer 102 is made of N-type aluminum gallium nitride (Alx10Ga1-x10N), a channel layer 103 is made of gallium nitride (GaN), and an insulating layer 104 is made of undoped aluminum nitride (AlN). On the insulating layer 104, a source electrode 10S and a drain electrode 10D are formed, and are in ohmic contact therewith. On the insulating layer 104, a gate electrode 10G is formed in a region between the source electrode 10S and the drain electrode 10D, and is in schottky contact therewith. An interface between the channel layer 103 and the electron supply layer 102 is a heterojunction interface of GaN/AlGaN, and an interface between the insulating layer 104 and the channel layer 103 is also a heterojunction interface of AlN/GaN. A semiconductor device in which both an upper and lower interfaces of the channel layer 103 are formed of a heterojunction interface like that of such AlN/GaN/AlGaN is referred to as a semiconductor device having a double heterostructure.
FIG. 11 is a cross-sectional view schematically showing band diagram of a conduction band in the region directly beneath the gate electrode 10G, in the field effect transistor type semiconductor device having a double heterostructure illustrated in FIG. 10. There are differences (band discontinuities) ΔEc(AlGaN/GaN) and ΔEc(AlN/GaN) in conduction band edge energy Ec between GaN and AlGaN, and between GaN and AlN, respectively. Amounts of the band discontinuities are set as ΔEc(AlN/GaN)>ΔEc(AlGaN/GaN). In the double heterostructure, a two-dimensional electron gas 107 is produced in the vicinity of the interface of the GaN channel layer 103 with the AlGaN electron supply layer 102 and in the vicinity of the interface of the GaN channel layer 103 with the AlN insulating layer 104. In the structure shown in FIG. 10, a band gap Eg(AlN) of AlN composing the insulating layer 104 is large, compared with a band gap Eg(GaN) of GaN, and thereby, a schottky barrier ΦB is increased. Accordingly, there is provided such advantage that the forward gate breakdown voltage of the field effect transistor type semiconductor device is improved thereby.
Examples of a field effect transistor type semiconductor device having a double heterostructure have been reported as described below.
Imanaga et al. also have reported such a field effect transistor type semiconductor device having a double heterostructure which adopts a laminated structure of an AlN layer and a silicon dioxide (SiO2) layer as an insulating layer, instead of an AlN insulating layer (see Patent Document 2).
Yosida has reported a semiconductor device having a double heterostructure of AlGaN/GaN/AlGaN in which an AlN insulating layer is replaced with undoped AlGaN (sec Patent Document 3). O. Aktas et al. also describe a semiconductor device having a double heterostructure of AlGaN/GaN/AlGaN in which an AlN insulating layer is replaced with undoped AlGaN (sec Non-Patent Document 1).
Further, examples of a group III nitride-based semiconductor device employing a structure in which an insulating film is inserted between a gate electrode and a semiconductor layer have been reported as described below.
Matuo et al. have reported a semiconductor device in which a silicon nitride (SiN) insulating film is provided on a double heterostructure of GaN/N-type AlGaN/GaN (see Patent Document 4).
Further, Ching-Ting Lee et al. have reported a semiconductor device having a Metal-Insulator-Semiconductor (MIS) structure in which an insulating film having a laminated structure of gallium oxide (Ga2O3) and SiO2 is formed on an n-type GaN channel layer (sec Non-Patent Document 2).    Patent Document 1: JP2000-294768 A    Patent Document 2: JP2000-252458 A    Patent Document 3: JP11-261052 A    Patent Document 4: JP2004-335960 A    Non-Patent Document 1: O. Aktas et al., IEEE Electron Device Letters, Vol. 18, No. 6, pp. 293-295, June 1997    Non-Patent Document 2: Ching-Ting Lee et al., IEEE Electron Device Letters, Vol. 24, No. 2, pp. 54-56, February 2003